In the fabrication of semiconductor devices, many fin type field effect transistors (finFETs) rely on tall gate structures. Such structures may allow for a reduction in horizontal resistance, however, tall gate structures typically result in gate (PC) collapse, hugging gates, active (Rx) hole and gate cut (CT) tip to tip short. Consequently a SAC process can help avoid such problems. Furthermore, tall gate structures result in higher gate height budget due to trench silicide (TS) reactive-ion etching (RIE) selectivity and TS chemical-mechanical planarization (CMP), e.g., TS RIE and TS CMP can cause more than 35 nm of gate height loss.
A known approach for forming a conventional SAC cap layer includes forming a silicon nitride (SiN) layer over recessed gate structures, as depicted in FIG. 1. Referring to FIG. 1 (a cross-sectional view), a nitride layer 101 is formed, e.g., of SiN, as a protection layer over the recessed gates 103 and the spacers 105. However, the nitride layer 101 is incapable of preventing erosion of the gates 103 and spacers 105 during TS and contact etch stop layer (CESL) RIE for one or more of the reasons described above.
A need therefore exists for methodology for forming a bilayer SAC cap to prevent cap material and spacer erosion during subsequent TS and CELS RIE.